Trench-capacitor dynamic random access memory (DRAM) cells have recently been developed in a continuing effort to fit the maximum charge storage capacity into the smallest space. Most conventional DRAM cells of this type comprise a capacitor trench having a storage oxide grown on its sidewalls. A grounded capacitor electrode fills this trench, and an (n+) doped region surrounds the trench in the semiconductor layer and extends to form a source region for the corresponding field effect pass gate transistor. A (p) pass gate channel region connects this source region to an (n+) diffused drain region of the pass gate transistor.
An undesirably large space is required to be laid out between the side of the trench capacitor opposite the pass gate transistor and the next cell. This is because a parasitic transistor will otherwise form between the (n+) implantation surrounding the capacitor trench and the (n+) drain region of the next pass gate transistor. Prior art attempts to minimize these parasitic transistors include providing local oxide isolating structures that still take up an undesirably large amount of cell area.
More recently, Lu et al. have proposed a trench-capacitor memory cell that stores the charge on the trench electrode rather than in a surrounding diffused region (N. C. Lu, "A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's", IEEE Journal of Solid State Circuits, Vol. SC-21, No. 5, pages 627-633 (October, 1986)). In this cell, a conductive plate connects an upper surface of the capacitor electrode to an adjacent source region of the pass gate transistor, spanning the capacitor storage oxide on the surface of the epitaxial layer. A metallic bit line is coupled to a drain region of the pass gate transistor.
This proposed cell has the disadvantage of requiring at least two layers of metal or other conductor thus complicating the cell's fabrication. A need therefore exists for a minimum-dimension trench-capacitor DRAM cell that requires only one level of metal interconnect while at the same time avoiding the large spacing requirements of conventional cells between the trench capacitor and the pass gate transistor of the next adjacent cell.